Ruthwik Reddy Sunketa
PhD student at Advent Lab, ASU
Computer Engineering PhD student specializing in FPGA architecture, design, and automated EDA flows. Current research focuses on next-generation FPGA architectures for AI/ML workload acceleration and hardware-software co-design. Experience in digital design, verification, physical design, and EDA flow development.
Education
Publications
Introduced ATLAS, an automated flow that transforms high-level deep learning models directly into FPGA implementations without manual RTL work. The system pairs a compiler frontend that converts DL layers into architecture-agnostic GEMM function calls with a backend generator that produces optimized RTL wrappers with tiling and control logic. Evaluated across 11 designs, from individual layers (fully connected, convolution, attention) to complete models (CNNs, MLPs, Transformers), targeting FPGA architectures with specialized tensor acceleration hardware.
Proposed an architecture combining analog in-memory computing (IMC) blocks with FPGAs, replacing traditional ADCs with analog content-addressable memories (ACAMs) to enable nonlinear operations and dynamic matrix computations directly within IMC blocks. Conducted design-space exploration to optimize crossbar dimensions and developed efficient mapping strategies for attention-based models, achieving up to 40× higher energy efficiency and 4.1× higher area efficiency on CNN and Transformer benchmarks while maintaining robust performance on long input sequences.
Proposed a compiler-independent methodology that lets high-level synthesis tools access custom FPGA hardblocks directly from C/C++ source, treating architectural hardblocks as schedulable operators through an RTL blackbox abstraction with explicit latency and timing contracts. Evaluated on a Tensor Slice-based FPGA architecture using AMD Vitis HLS and the VTR toolchain, achieving lower area-delay product than behavioral HLS baselines and substantially higher productivity-adjusted efficiency than handwritten RTL.
Conducted design space exploration to integrate RRAM-based IMC engines into a custom FPGA fabric. Developed Verilog benchmarks for LeNet, ResNet, VGG, and Transformer Attention to evaluate AI workload performance. Achieved a 6.58× latency reduction and 8,741× energy efficiency gain over baseline FPGA for DNN inference.
Developed an iterative framework for FPGA verification that maximizes routing resource coverage. This work addresses the critical need for comprehensive verification methodologies in FPGA design flows.
Extended OpenFPGA framework to support hardened Network-on-Chips (NoCs) with arbitrary physical topologies. Developed a dedicated NoC bitstream generator and configuration mechanism to manage dynamic compile-time address translation and global routing mode selection. Evaluated NoC-based architectures through an automated RTL-to-bitstream flow, confirming a 3.66× frequency gain and 15% lower routing congestion for I/O-intensive workloads over traditional fabrics.